This invention relates to phase-locked loop circuitry for programmable logic devices. More particularly, this invention relates to a phase-locked loop circuit for a programmable logic device having greater flexibility in adjusting both frequency and phase of the output signal relative to those of the input signal.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output (xe2x80x9cI/Oxe2x80x9d) pins, with the connections of the pins to the interconnect structure also being programmable.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor-transistor logic (xe2x80x9cTTLxe2x80x9d), in which a logical xe2x80x9chighxe2x80x9d signal was nominally at 5 volts, while a logical xe2x80x9clowxe2x80x9d signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signalling schemes, such as LVTTL (Low Voltage TTL), PCI (Peripheral Component Interface), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants), LVDS (Low Voltage Differential Signalling), and others. Some of these signalling schemes, and particularly LVDS, require high-frequency clock signals with precise phase relationships for proper operation.
It is known to include phase-locked loop circuitry on programmable logic devices to help counteract xe2x80x9cskewxe2x80x9d and excessive delay in clock signals propagating on the device (see, for example, Jefferson U.S. Pat. No. 5,699,020 and Reddy et al. U.S. Pat. No. 5,847,617, both of which are hereby incorporated by reference herein in their entireties). For example, phase-locked loop circuitry may be used to produce a clock signal which is advanced in time relative to a clock signal applied to the programmable logic device. The advanced clock signal is propagated to portions of the device that are relatively distant from the applied clock signal so that the propagation delay of the advanced clock signal brings it back into synchronism with the applied clock signal when it reaches the distant portions of the device. In this way all portions of the device receive synchronous clock signals and clock signal xe2x80x9cskewxe2x80x9d (different amounts of delay in different portions of the device) is reduced.
However, while phase-locked loops are accurate sources of clock signals, they generally are limited in the frequencies they can provide, both in terms of adjustability, and in terms of the absolute range of frequencies that can be generated. Moreover, the ability to adjust the phase of the output clock signal relative to the input clock signal is limited.
It would be desirable to be able to provide a phase-locked loop circuit that is adjustable in phase and can generate a wide range of frequencies.
It would be particularly desirable to be able to provide such a phase-locked loop circuit on a programmable logic device, especially to provide a clock signal for a high-speed signalling scheme, such as LVDS.
It is an object of this invention to attempt to provide a phase-locked loop circuit that is adjustable and can generate a wide range of frequencies.
It is a particular object of this invention to attempt to provide such a phase-locked loop circuit on a programmable logic device, especially to provide a clock signal for a high-speed signalling scheme, such as LVDS.
In accordance with the present invention, there is provided a phase-locked loop circuit having an input terminal for accepting an input clock signal, a phase/frequency detector having a signal input connected to the input terminal, a phase/frequency detection input and a signal output, a charge pump having a pump input connected to the signal output of the phase/frequency detector and having a pump output, and a voltage-controlled oscillator having an oscillator input connected to the pump output, an oscillator output, and a plurality of signal taps. The signal taps are separated from one another in phase by substantially uniform delays. A feedback loop feeds back to the phase detection input a signal from one of the signal taps. The feedback loop has a feedback multiplexer for selecting that one of the signal taps to feed back. An output multiplexer selects one of the signal taps as an output signal of the phase-locked loop. When the output multiplexer selects a first signal tap and the feedback multiplexer selects a subsequent one of the signal taps separated from the first signal tap by an odd number of signal taps, the output signal has a phase that is advanced relative to the input clock signal by an even multiple (specifically, one more than the odd number of signal taps) of the substantially uniform delay. When the feedback multiplexer selects a first signal tap and the output multiplexer selects a subsequent one of the signal taps separated from the first signal tap by an odd number of signal taps, the output signal has a phase that is retarded relative to the input clock signal by an even multiple (specifically, one more than the odd number of signal taps) of the substantially uniform delay.
In addition, either with or without the feedback and output multiplexers, the phase-locked loop includes a programmable pre-scale counter at the input terminal, a programmable post-scale counter downstream of the output multiplexer and a programmable feedback-scale counter downstream of the feedback multiplexer in the feedback loop. Each of the counters is loadable or programmable with an integer value. The pre-scale counter divides the frequency of the output signal by the integer value programmed therein, the post-scale counter divides the frequency of the output signal by the integer value programmed therein, and the feedback-scale counter multiplies the frequency of the output signal by the integer value programmed therein.
Such a phase-locked loop circuit can be adjusted to provide almost any rational multiple of the input frequency by correctly choosing the integers loaded into the various counters. If the feedback-scale counter is loaded with integer M, the pre-scale counter is loaded with integer N and the post-scale counter is loaded with integer K, then the output frequency equals the input frequency multiplied by M/(NK). Thus, the phase-locked loop circuit can be used as a general purpose frequency synthesizer.
The voltage-controlled oscillator preferably is a ring oscillator having an odd number of stages each of which is essentially an inverter. The phase delay that is characteristic of the operation of a phase-locked loop derives from the cumulative delays of the inverters. Therefore, the relative phase of the output signal can be adjusted by tapping the voltage-controlled oscillator for feedback and output signals at the correct stages.
Thus, if the two signals are tapped from two stages having one stage between them, the output signal will differ in phase from the input signal by the phase delay of two stages. This is the minimum possible phase shift unit, because while the outputs of two adjacent taps differ by the delay of one stage, they are also inverted relative to one another, adding 180xc2x0 to the phase shift between them. For example, if the output of one stage is a rising edge, the output of the next stage, though delayed by only one additional delay, would be a falling edge.
Whether the output signal leads or lags the input signal in phase is determined by whether the feedback signal is tapped upstream or downstream of where the output signal is tapped. When the output signal is tapped from a first signal tap and the feedback signal is tapped from a subsequent tap, the output signal has a phase that is advanced relative to the input clock signal. When the feedback signal is tapped from a first signal tap and the output signal is tapped from a subsequent tap, the output signal has a phase that is retarded relative to the input clock signal. However, it will be recognized that whether one signal leads another by a particular phase angle, or lags the other by 360xc2x0 minus that phase angle, is relative, and might have to be determined based on other signals.
In addition, the phase-locked loop circuit preferably has an alternate output that bypasses the post-scale counter. Therefore, the circuit actually has two outputs, both having the same phase, but one having a frequency K times the other.
One limitation on the phase-locked loop circuit as a general frequency synthesizer is that even though the ratio M/(NK) may be a small number, any individual one of the factors M, N and K may be large, meaning that in a particular portion of the circuit, the frequency may be very high or very low. Care must be taken not to choose M, N or K so large that the intermediate frequencies are too high or low for the circuit components to handle.
For example, assume that it is desired to use the phase-locked loop circuit to convert signals from the conventional xe2x80x9cT1xe2x80x9d telecommunications data rate to the conventional xe2x80x9cE1xe2x80x9d telecommunications data rate. T1 operates at 1.544 MHZ; E1 operates at 2.048 MHZ. To produce an E1 clock signal from a T1 clock signal requires the T1 clock signal frequency to be multiplied by approximately 1.326, or more specifically by the rational number 256/193. This can implemented, using the counters, as a multiplication by 256, followed by a division by 193, or alternatively as a division by 193 followed by a multiplication by 256. The first approach is to use the xe2x80x9cdivide by Nxe2x80x9d pre-scale counter to divide the incoming T1 clock signal frequency by 193. Then the xe2x80x9cdivide by Mxe2x80x9d feedback-scale counter is used to force the phase/frequency detector and voltage-controlled oscillator to multiply the signal frequency from the pre-scale counter by 256. The xe2x80x9cdivide by Kxe2x80x9d post-scale counter is bypassed (or loaded with the value xe2x80x9c1xe2x80x9d). A possible problem with this approach is that the phase/frequency detector is receiving an 8 kHz signal from the pre-scale counter (because 1.544 MHZ÷193=8 kHz). 8 kHz is a relatively low frequency that may be below the minimum acceptable input frequency for the phase/frequency detector. Care must be taken to build the phase-locked loop circuit with components that will function at frequencies that low or lower if they are expected.
The second approach is to bypass the xe2x80x9cdivide by Nxe2x80x9d pre-scale counter (or load it with the value xe2x80x9c1xe2x80x9d) and use the xe2x80x9cdivide by Mxe2x80x9d feedback-scale counter to force the phase/frequency detector and voltage-controlled oscillator to multiply the incoming T1 clock signal frequency by 256. This produces a voltage-controlled oscillator output signal having a frequency of approximately 395 MHZ. The xe2x80x9cdivide by Kxe2x80x9d post-scale counter is then used to divide the voltage-controlled oscillator output signal frequency by 193. A possible problem with this approach is that 395 MHZ is a relatively high frequency. Care must be taken to build the phase-locked loop circuit with components that will function at frequencies that high or higher if they are expected.
A further advantage of having both the xe2x80x9cdivide by Nxe2x80x9d pre-scale counter and the xe2x80x9cdivide by Kxe2x80x9d post-scale counter is the ability to perform some of the division as a pre-scale operation and some of the division as a post-scale operation. That could be advantageous in a situation where the factor by which the frequency is to be divided is so high that performing the division at the input would mean that the input frequency to the phase/frequency detector from the xe2x80x9cdivide by Nxe2x80x9d pre-scale counter would be too low as described above, but leaving the division for the xe2x80x9cdivide by Kxe2x80x9d post-scale counter would mean that the input frequency to the phase/frequency detector from the xe2x80x9cdivide by Mxe2x80x9d feedback-scale counter would be too high as discussed above. Breaking the division operation down into pre-scale and post-scale operations can be done as long as the factor by which the frequency is to be divided (xe2x80x9cfrequency divisorxe2x80x9d) is not a prime number, so that there are two non-unity integer factors to be loaded into the pre-scale and post-scale counters. (In the example set forth above, the frequency divisor is a prime number, so this alternative would not be available.)